Reductions in the size and inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of metal-oxide-semiconductor (MOS) devices, stress may be introduced in the channel region of a MOS transistor to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is to grow silicon-germanium (SiGe) stressors in source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate; forming spacers on sidewalls of the gate stack; forming recesses in the silicon substrate along the gate spacers; epitaxially growing SiGe stressors in the recesses, and then annealing. Since SiGe has a greater lattice constant than silicon has, it expands after annealing and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The conventional stressor formation processes suffer drawbacks, however. Boron is a commonly used p-type impurity for source/drain regions and lightly doped source/drain regions. To reduce sheet resistance, it is preferred that the boron concentration is high. However, the addition of boron has the effect of reducing lattice constant, and thus with a higher boron concentration, the strain introduced by SiGe stressors becomes more relaxed. In addition, a high boron concentration results in more boron to be diffused into channel regions, and the short channel characteristics are adversely affected.
Therefore, new methods for preserving a high boron concentration in MOS devices without incurring the drawbacks are needed.